Login / Signup

Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability.

K. WatanabeT. ShimadaK. HiroseH. ShindoD. KobayashiTakaho TanigawaShoji IkedaTakamitsu ShinadaHiroki KoikeTetsuo EndohT. MakinoTakeshi Ohshima
Published in: IRPS (2022)
Keyphrases
  • design space
  • case study
  • real time
  • neural network
  • artificial intelligence
  • e learning
  • low power
  • estimation error
  • design decisions
  • information systems
  • learning environment
  • failure rate
  • circuit design
  • single chip