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Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros.
Ryusuke Nebashi
Noboru Sakimura
Tadahiko Sugibayashi
Naoki Kasai
Published in:
IEICE Trans. Electron. (2009)
Keyphrases
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high speed
selection strategy
read write
selection scheme
key features
integrated circuit
design considerations
replication scheme
real time
data partitioning
load balancing
data structure
high capacity
disk drives
channel capacity
information leakage
neural network