Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks.
Naoya OnizawaHooman JarollahiTakahiro HanyuWarren J. GrossPublished in: IEEE J. Emerg. Sel. Topics Circuits Syst. (2016)
Keyphrases
- hardware implementation
- associative memory
- multiple valued
- hardware architecture
- processing elements
- signal processing
- efficient implementation
- alpha beta
- file organization
- multi valued
- image processing algorithms
- field programmable gate array
- boolean functions
- complex valued
- parallel architecture
- neural network
- high dimensional
- continuous attributes