Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic.
Naoya OnizawaDuckgyu ShinTakahiro HanyuPublished in: FLAP (2020)
Keyphrases
- learning algorithm
- chip design
- low cost
- circuit design
- digital circuits
- delay insensitive
- floating gate
- rbf network
- learning tasks
- single chip
- training data
- hardware and software
- multi layered
- low power
- input image
- active learning
- machine learning
- learning scheme
- real time
- power consumption
- reinforcement learning
- high speed
- back propagation
- power supply
- hardware implementation
- logic programming
- training examples
- machine learning algorithms
- document images
- decision trees
- learning rate
- computer systems
- activation function
- random access memory
- image sensor
- single layer
- silicon on insulator
- processing capabilities
- classical logic
- supervised learning
- semi supervised
- training set
- image processing
- neural network