Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic.
Duckgyu ShinNaoya OnizawaWarren J. GrossTakahiro HanyuPublished in: IEEE Access (2020)
Keyphrases
- low cost
- chip design
- circuit design
- neural network
- delay insensitive
- training set
- digital circuits
- training algorithm
- real time
- single chip
- image processing
- high speed
- hardware and software
- training process
- classical logic
- modal logic
- power consumption
- training samples
- computer systems
- training data
- low power
- massively parallel
- computer software
- asynchronous circuits
- object detection
- artificial neural networks