DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks.
Jan SommerM. Akif ÖzkanOliver KeszöczeJürgen TeichPublished in: FPL (2022)
Keyphrases
- digital signal processing
- verilog hdl
- signal processing
- systolic array
- real time image processing
- digital signal processor
- high speed
- digital signal
- field programmable gate array
- data flow
- real time
- image processing
- low power
- computer vision and image processing
- texas instruments
- digital signal processors
- database
- hardware implementation
- floating point
- packing problem
- parallel architecture
- data acquisition
- low cost
- computer vision
- data sets