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: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable Architecture.
François Philipp
Manfred Glesner
Published in:
FPL (2012)
Keyphrases
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coarse grained
reconfigurable architecture
fine grained
direct manipulation
systolic array
bitstream
high level
bit rate
shared memory
artificial intelligence
machine learning
image segmentation
hiv protease