César Albenes Zeferino

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 11

Top Topics

Resolution Enhancement

Modular Exponentiation

Top Venues

J. Sens. Actuator Networks

Publications

Lucas Amilton Martins, Felipe Viel, Laio Oriel Seman, Eduardo Augusto Bezerra, César Albenes Zeferino
A real-time SVM-based hardware accelerator for hyperspectral images classification in FPGA. Microprocess. Microsystems 104 (2024)
Rubens Vicente De Liz Bomer, César Albenes Zeferino, Laio Oriel Seman, Valderi Reis Quietinho Leithardt
Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers. IEEE Access 11 (2023)
Felipe Viel, Renato Cotrim Maciel, Laio Oriel Seman, César Albenes Zeferino, Eduardo Augusto Bezerra, Valderi Reis Quietinho Leithardt
Hyperspectral Image Classification: An Analysis Employing CNN, LSTM, Transformer, and Attention Mechanism. IEEE Access 11 (2023)
Arielle Verri Lucca, Guilherme A. M. Sborz, Valderi R. Q. Leithardt, Marko Beko, César Albenes Zeferino, Wemerson Delcio Parreira
A Review of Techniques for Implementing Elliptic Curve Point Multiplication on Hardware. J. Sens. Actuator Networks 10 (1) (2021)
Douglas Rossi Melo, César Albenes Zeferino, Eduardo Augusto Bezerra, Luigi Dilillo
Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router. DTIS (2021)
Felipe Viel, Wemerson Delcio Parreira, Altamiro Amadeu Susin, César Albenes Zeferino
A Hardware Accelerator for Onboard Spatial Resolution Enhancement of Hyperspectral Images. IEEE Geosci. Remote. Sens. Lett. 18 (10) (2021)
Felipe Viel, Luis Augusto Silva, Valderi Reis Quietinho Leithardt, Juan Francisco De Paz Santana, Raimundo Celeste Ghizoni Teive, César Albenes Zeferino
An Efficient Interface for the Integration of IoT Devices with Smart Grids. Sensors 20 (10) (2020)
Douglas Almeida dos Santos, Lucas Matana Luza, César Albenes Zeferino, Luigi Dilillo, Douglas Rossi de Melo
A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems. DTIS (2020)
Luiz Fernando Heidrich Duarte, César Albenes Zeferino, Raimundo Celeste Ghizoni Teive
An Architecture for Delivering Graphical Web Applications in Constrained IoT Devices. SBESC (2019)
Douglas Rossi de Melo, César Albenes Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra
Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router. LATS (2019)
Marcos Roberto Silva, César Albenes Zeferino
Confidentiality and Authenticity in a Platform Based on Network-on-Chip. SBESC (2017)
Paulo Viníccius Vieira, César Albenes Zeferino, André Luís Alice Raabe
Avaliação Empírica da Proposta Interdisciplinar de Uso dos Processadores BIP. Revista Brasileira de Informática na Educ. 23 (2) (2015)
César Albenes Zeferino, Sidnei Baron, Michelle Silva Wangham
Segurança em Redes-em-Chip: Conceitos e Revisão do Estado da Arte. RITA 21 (1) (2014)
Sidnei Baron, Michelle Silva Wangham, César Albenes Zeferino
Security mechanisms to improve the availability of a Network-on-Chip. ICECS (2013)
Paulo Viníccius Vieira, André Luis Alice Raabe, César Albenes Zeferino
Bipide - Ambiente de Desenvolvimento Integrado para a Arquitetura dos Processadores BIP. Revista Brasileira de Informática na Educ. 18 (1) (2010)
Marcelo Daniel Berejuck, César Albenes Zeferino
Adding mechanisms for QoS to a network-on-chip. SBCCI (2009)
César Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin
RASoC: A Router Soft-Core for Networks-on-Chip. DATE (2004)
César Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin
ParIS: a parameterizable interconnect switch for networks-on-chip. SBCCI (2004)
César Albenes Zeferino, Altamiro Amadeu Susin
SoCIN: A Parametric and Scalable Network-on-Chip. SBCCI (2003)
Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, César Albenes Zeferino
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network. DATE (2003)
Márcio Eduardo Kreutz, César Albenes Zeferino, Luigi Carro, Altamiro Amadeu Susin
Análise e Seleção de Redes de Interconexão para Síntese de Sistemas no Ambiente S3E2S. RITA 8 (1) (2001)