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A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology.
Aibin Yan
Zhen Zhou
Shaojie Wei
Jie Cui
Yong Zhou
Tianming Ni
Patrick Girard
Xiaoqing Wen
Published in:
ACM Great Lakes Symposium on VLSI (2022)
Keyphrases
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highly robust
cmos technology
low power
power consumption
low delay
three dimensional
low cost
design process
power dissipation
spatio temporal