Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS.
Aibin YanLitao WangJie CuiZhengfeng HuangTianming NiPatrick GirardXiaoqing WenPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2024)
Keyphrases
- power consumption
- low power
- high speed
- nm technology
- flip flops
- random access memory
- low cost
- magnetic field
- recovery algorithm
- cmos technology
- xml documents
- read write
- power dissipation
- solid state
- image sensor
- design considerations
- tree structure
- single chip
- image recovery
- high density
- graph structure
- power reduction
- directed graph
- decision trees
- silicon on insulator