Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications.
Aibin YanJing XiangZhengfeng HuangTianming NiJie CuiPatrick GirardXiaoqing WenPublished in: ITC-Asia (2023)
Keyphrases
- low power
- power consumption
- highly reliable
- single chip
- low cost
- safety critical
- high speed
- vlsi architecture
- low power consumption
- cmos technology
- digital signal processing
- power reduction
- gate array
- embedded systems
- logic circuits
- power dissipation
- mixed signal
- ultra low power
- design process
- design methodology
- knowledge based systems
- real time
- image sensor
- support systems
- intelligent agents