Impact of Aging on Soft Error Susceptibility in CMOS Circuits.

Ambika Prasad Shah Patrick Girard

Published in: IOLTS (2020)

Keyphrases

analog vlsi
high speed
circuit design
delay insensitive
vlsi circuits
cmos technology
error rate
floating gate
power consumption
low cost
power dissipation
low power
age estimation
random access memory
error bounds
chip design
digital circuits
power supply
relative error
age related
real time