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Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS.

Aibin YanShukai SongJixiang ZhangJie CuiZhengfeng HuangTianming NiXiaoqing WenPatrick Girard
Published in: ITC-Asia (2022)
Keyphrases
  • power consumption
  • low power
  • low cost
  • high speed
  • robust estimation
  • tree structure
  • cost sensitive
  • estimation error
  • minimum cost
  • path length
  • cost reduction