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High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology.
Aibin Yan
Zhen Zhou
Liang Ding
Jie Cui
Zhengfeng Huang
Xiaoqing Wen
Patrick Girard
Published in:
DATE (2023)
Keyphrases
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low power
cmos technology
power consumption
embedded dram
high speed
flip flops
low cost
spl times
low voltage
single chip
power dissipation
random access memory
power management
parallel processing
digital signal processing
multi view
real time