A defect-tolerant cluster in a mesh SRAM-based FPGA.
Arwa Ben DhiaSaif-Ur RehmanAdrien BlanchardonLirida A. B. NavinerMounir BenabdenbiRoselyne Chotin-AvotEmna AmouriHabib MehrezZied MarrakchiPublished in: FPT (2013)
Keyphrases
- field programmable gate array
- clustering algorithm
- d mesh
- power consumption
- high speed
- data transmission
- low cost
- hierarchical structure
- power reduction
- real time
- hardware implementation
- real time image processing
- low power consumption
- cluster analysis
- data acquisition
- parallel hardware
- verilog hdl
- defect detection
- hierarchical clustering
- parallel architecture
- digital signal processing
- low power
- mesh generation
- data clustering
- signal processing
- data sets