Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA.
Emna AmouriZied MarrakchiHabib MehrezPublished in: ReCoSoC (2011)
Keyphrases
- signal processing
- digital signal
- load distribution
- high speed
- hardware implementation
- routing problem
- pairwise
- routing protocol
- interconnection networks
- real time image processing
- routing algorithm
- d mesh
- shortest path
- flip flops
- primal dual
- ad hoc networks
- load balancing
- low cost
- field programmable gate array
- network topology
- fpga implementation
- inter domain
- real time
- national library of medicine
- verilog hdl
- hardware architectures
- software implementation
- hardware design
- response time
- image processing