Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires.
Sonda ChtourouZied MarrakchiEmna AmouriVinod PangraciousMohamed AbidHabib MehrezPublished in: Microprocess. Microsystems (2016)
Keyphrases
- interconnection networks
- high speed
- routing algorithm
- hardware architecture
- hardware implementation
- hardware design
- fault tolerant
- software implementation
- parallel algorithm
- real time
- hierarchical architecture
- parallel architecture
- parallel computers
- hardware architectures
- xilinx virtex
- fpga technology
- field programmable gate array
- packet switching
- hierarchical structure
- message passing
- reconfigurable hardware
- low cost
- management system
- fpga implementation
- coarse to fine
- dedicated hardware
- significant improvement
- systolic array
- arbitrary topology
- ad hoc networks
- small world
- routing protocol
- signal processing
- pipelined architecture