On wiring delays reduction of tree-based FPGA using 3-D fabric.

Vinod Pangracious Mohamed Sahbi Marrakchi Habib Mehrez Zied Marrakchi

Published in: SoCC (2014)

Keyphrases

field programmable gate array
integrated circuit
power reduction
real time
high density
verilog hdl
real time image processing
reduction method
building blocks
high speed
information systems
embedded systems
data acquisition
signal processing
state information
evolutionary algorithm
digital signal