Architecture level TSV count minimization methodology for 3D tree-based FPGA.
Vinod PangraciousHabib MehrezZied MarrakchiPublished in: COOL Chips (2013)
Keyphrases
- hardware implementation
- real time
- hardware architecture
- hardware design
- management system
- fpga implementation
- levels of abstraction
- design methodology
- objective function
- software implementation
- low cost
- network architecture
- high speed
- hardware architectures
- fpga technology
- pipelined architecture
- formal model
- field programmable gate array
- data acquisition
- quality of service
- digital signal
- xilinx virtex