Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor.
Hai YuMichael NicolaidisLorena AnghelNacer-Eddine ZergainohPublished in: ETS (2011)
Keyphrases
- low power
- high speed
- fault detection
- low power consumption
- digital signal processing
- single chip
- power consumption
- low cost
- gate array
- vlsi architecture
- fault diagnosis
- industrial processes
- vlsi circuits
- power reduction
- high power
- pattern recognition
- power dissipation
- image sensor
- wireless transmission
- tennessee eastman
- failure detection
- fault detection and diagnosis
- fault identification
- robust fault detection
- cmos technology
- logic circuits
- real time
- genetic algorithm
- mixed signal
- evolutionary computation
- image processing
- artificial intelligence