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Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology.
M. Saliva
Florian Cacho
C. Ndiaye
Vincent Huard
D. Angot
Alain Bravaix
Lorena Anghel
Published in:
IRPS (2015)
Keyphrases
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cmos technology
leakage current
low voltage
low power
logic circuits
random access memory
power consumption
power dissipation
spl times
low cost
power line
high speed
flip flops
parallel processing
image sensor
design considerations
power management
mixed signal
embedded dram
multi valued