Eric Belhaire

Publication Activity (10 Years)

Years Active: 1988-2009
Publications (10 Years): 0

Publications

Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. ACM Trans. Reconfigurable Technol. Syst. 2 (2) (2009)
Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer
Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit. ACM Trans. Embed. Comput. Syst. 9 (2) (2009)
Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer
Spintronic Device Based Non-volatile Low Standby Power SRAM. ISVLSI (2008)
Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert
TAS-MRAM based Non-volatile FPGA logic circuit. FPT (2007)
Guillaume Prenat, Mourad El Baraji, Wei Guo, Ricardo Sousa, Liliana Buda-Prejbeanu, Bernard Dieny, Virgile Javerliac, Jean-Pierre Nozieres, Weisheng Zhao, Eric Belhaire
CMOS/Magnetic Hybrid Architectures. ICECS (2007)
Jacques-Olivier Klein, Eric Belhaire, Claude Chappert, Florent Ouchet, Russell Cowburn, Dan Read, Dorothee Petit
Synthesis of Finite State Machines with Magnetic Domain Wall Logic. ISCAS (2007)
Amir Kazéminéjad, Eric Belhaire
Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications. DFT (2001)
Antoine Dupret, Eric Belhaire, Jean-Claude Rodier, Philippe Lalanne, Donald PrCvost, Patrick Garda, Pierre Chavel
An optoelectronic CMOS circuit implementing a simulated annealing algorithm. IEEE J. Solid State Circuits 31 (7) (1996)
A. Reichart, Patrick Garda, Eric Belhaire, Francis J. Devos, Bertrand Y. Zavidovique
A 60x60 Processor Array Smart Sensor for Binary Image Processung. MVA (1988)