An adaptive serial-parallel CAM architecture for low-power cache blocks.
Aristides EfthymiouJim D. GarsidePublished in: ISLPED (2002)
Keyphrases
- low power
- vlsi architecture
- power consumption
- low cost
- high speed
- cmos technology
- mixed signal
- multithreading
- single chip
- wireless transmission
- nm technology
- digital signal processing
- parallel processing
- vlsi circuits
- signal processor
- low power consumption
- delay insensitive
- high power
- computer architecture
- parallel computing
- logic circuits
- level parallelism
- parallel computers
- real time
- distributed memory
- block size
- parallel implementation
- data flow
- motion estimation