Yuanlong Xiao

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 15

Top Topics

Parallel Implementation

Real Time Image Processing

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Yuanlong Xiao, Dongjoon Park, Zeyu Jason Niu, Aditya Hota, André DeHon
ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation. ACM Trans. Reconfigurable Technol. Syst. 17 (2) (2024)
Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Dongjoon Park, Zhijing Yao, Yuanlong Xiao, André DeHon
Asymmetry in Butterfly Fat Tree FPGA NoC. ICFPT (2023)
Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development. ASPLOS (2022)
Dongjoon Park, Yuanlong Xiao, André DeHon
Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration. FPT (2022)
Yuanlong Xiao, André DeHon
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers. FPGA (2022)
Yuanlong Xiao, Aditya Hota, Dongjoon Park, André DeHon
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. FPL (2022)
Eric Micallef, Yuanlong Xiao, André DeHon
HLS-Compatible, Embedded-Processor Stream Links. FCCM (2021)
André DeHon, Hans Giesen, Nik Sultana, Yuanlong Xiao
Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation. CoRR (2021)
Yuanlong Xiao, Syed Tousif Ahmed, André DeHon
Fast Linking of Separately-Compiled FPGA Blocks without a NoC. FPT (2020)
Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Jian Wang, Jinmei Lai
Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. FPGA (2019)
Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. FPT (2019)
Zhengjie Li, Yuanlong Xiao, Yufan Zhang, Yunbing Pang, Chengyu Hu, Jian Wang, Jinmei Lai
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. ACM Great Lakes Symposium on VLSI (2019)
Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, André DeHon
Case for Fast FPGA Compilation Using Partial Reconfiguration. FPL (2018)
Yuanlong Xiao, Jian Wang, Jinmei Lai
A universal automatic on-chip measurement of FPGA's internal setup and hold times. IEICE Electron. Express 13 (23) (2016)
Yuanlong Xiao, Jian Wang, Jinmei Lai
A power efficient current-mode differential driver for FPGAs. ASICON (2015)