HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation.
Yuanlong XiaoAditya HotaDongjoon ParkAndré DeHonPublished in: FPL (2022)
Keyphrases
- high level
- low level
- incremental learning
- high speed
- hardware implementation
- incremental version
- higher level
- real time
- fpga hardware
- field programmable gate array
- lower level
- signal processing
- source code
- manufacturing systems
- low cost
- intermediate level
- systolic array
- conceptual model
- semantic information
- mid level
- knowledge compilation
- hardware design
- software implementation
- real time image processing
- software engineering
- hardware architectures
- database