Fast Linking of Separately-Compiled FPGA Blocks without a NoC.
Yuanlong XiaoSyed Tousif AhmedAndré DeHonPublished in: FPT (2020)
Keyphrases
- network on chip
- hardware implementation
- high speed
- routing algorithm
- multi processor
- field programmable gate array
- real time image processing
- real time
- hardware architecture
- image blocks
- signal processing
- block size
- dct coefficients
- low cost
- fpga implementation
- hardware design
- single chip
- systolic array
- xilinx virtex
- packet switched
- digital signal
- digital signal processing
- parallel architecture
- intrusion detection
- image processing