Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks.
Yuanlong XiaoDongjoon ParkAndrew ButtHans GiesenZhaoyang HanRui DingNevo MagneziRaphael RubinAndré DeHonPublished in: FPT (2019)
Keyphrases
- building blocks
- field programmable gate array
- hardware implementation
- high speed
- real time image processing
- real time
- dedicated hardware
- low cost
- power reduction
- hardware design
- verilog hdl
- hardware architecture
- fpga implementation
- programmable logic
- data sets
- systolic array
- parallel hardware
- digital signal
- neural network
- low power consumption
- efficient implementation
- information retrieval
- pattern recognition
- relational databases
- signal processing
- parallel computing
- pipelined architecture
- integrity constraints