Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS.
Stefano Di CarloGiulio GambardellaMarco IndacoPaolo PrinettoDaniele RolfoPascal TrottaPublished in: FPL (2013)
Keyphrases
- field programmable gate array
- hardware implementation
- response time
- fpga implementation
- high speed
- manufacturing systems
- dynamically changing
- genetic algorithm
- information systems
- image sequences
- evolutionary algorithm
- real time
- dynamic environments
- orders of magnitude
- information retrieval
- machine learning
- neural network