Valentino Peluso

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 31

Top Topics

Avoid Overfitting

Image Classification

Depth Perception

Top Venues

VLSI-SoC (Selected Papers)

Publications

Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii, Paolo Montuschi
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning. IEEE Internet Things J. 11 (4) (2024)
Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii
Communication-Efficient Federated Learning With Gradual Layer Freezing. IEEE Embed. Syst. Lett. 15 (1) (2023)
Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii
Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference Services. ISLPED (2023)
Giacomo Zema, Valentino Peluso, Andrea Calimera, Enrico Macii
Concurrent Pipeline Stages Optimization for Embedded Keyword Spotting. AIIoT (2023)
Antonio Cipolletta, Valentino Peluso, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia
Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs. IEEE Internet Things J. 9 (1) (2022)
Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia
Monocular Depth Perception on Microcontrollers for Edge Applications. IEEE Trans. Circuits Syst. Video Technol. 32 (3) (2022)
Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii
Adaptive Test-Time Augmentation for Low-Power CPU. CoRR (2021)
Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii
On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets. VLSI-SoC (Selected Papers) (2021)
Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets. VLSI-SoC (2021)
Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets. IEEE Trans. Circuits Syst. II Express Briefs 68 (2) (2021)
Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia
Enabling monocular depth perception at the very edge. CVPR Workshops (2020)
Valentino Peluso, Enrico Macii, Andrea Calimera
Optimization Tools for ConvNets on the Edge. VLSI-SOC (2020)
Matteo Grimaldi, Valentino Peluso, Andrea Calimera
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. AICAS (2020)
Matteo Grimaldi, Valentino Peluso, Andrea Calimera
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. CoRR (2019)
Valentino Peluso, Roberto Giorgio Rizzo, Antonio Cipolletta, Andrea Calimera
Inference on the Edge: Performance Analysis of an Image Classification Task Using Off-The-Shelf CPUs and Open-Source ConvNets. SNAMS (2019)
Matteo Grimaldi, Valentino Peluso, Andrea Calimera
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores. IEEE Access 7 (2019)
Valentino Peluso, Antonio Cipolletta, Francesco Vaiana, Andrea Calimera
Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores. ICECS (2019)
Valentino Peluso, Matteo Grimaldi, Andrea Calimera
Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors. VLSI-SoC (2019)
Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Stefano Mattoccia
Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms. DATE (2019)
Valentino Peluso, Andrea Calimera
Energy-Driven Precision Scaling for Fixed-Point ConvNets. VLSI-SoC (2018)
Daniele Jahier Pagliari, Valentino Peluso, Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino
All-digital embedded meters for on-line power estimation. DATE (2018)
Valentino Peluso, Andrea Calimera
Scalable-effort ConvNets for multilevel classification. ICCAD (2018)
Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. DATE (2018)
Valentino Peluso, Andrea Calimera
Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis. VLSI-SoC (Selected Papers) (2018)
Valentino Peluso, Andrea Calimera
Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets. ISCAS (2018)
Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. ISCAS (2018)
Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling. VLSI-SoC (Selected Papers) (2017)
Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou, Xin Liu
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS. VLSI-SoC (2017)
Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping. VLSI-SoC (Selected Papers) (2016)
Valentino Peluso, Andrea Calimera, Enrico Macii, Massimo Alioto
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. VLSI-SoC (2016)
Alberto Bolzoni, Alessio La Bella, Davide Moschetta, Giulia Musacci, Giambattista Gruosso, Giancarlo Storti Gajani, Marco Aimo Boot, Luca Bellini, Alessio Canepa, Davide Cardella, Valentino Peluso, Paolo Guglielmi
Object based modelling of hybrid electrical vehicle and power management control. RTSI (2015)
Augusto Manuel Marques, Valentino Peluso, Michiel Steyaert, Willy M. C. Sansen
Analysis of the trade-off between bandwidth, resolution, and power in ΔΣ analog to digital converters. ICECS (1998)