Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.
Deblina SarkarSamiran GangulyDeepanjan DattaA. Ananda Prasad SarabSudeb DasguptaPublished in: VLSI Design (2007)
Keyphrases
- low power
- high speed
- power consumption
- nano scale
- logic circuits
- cmos technology
- power reduction
- low cost
- energy dissipation
- gate array
- vlsi circuits
- power dissipation
- single chip
- high power
- ultra low power
- wireless transmission
- digital signal processing
- vlsi architecture
- delay insensitive
- data acquisition
- digital government
- low power consumption
- mixed signal
- image sensor
- nm technology
- power saving
- rfid tags
- parallel processing