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Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET.
Ramesh Vaddi
Sudeb Dasgupta
R. P. Agarwal
Published in:
ISVLSI (2011)
Keyphrases
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field effect transistors
feature extraction
multiple input
machine learning
low level
image features
objective function
object detection
nano scale
neural network
high level
training set
feature vectors
support vector machine
negative effects
factorial design