Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing.
Sadulla ShaikKalva Sri Rama KrishnaRamesh VaddiPublished in: VLSI Design (2016)
Keyphrases
- energy efficient
- wireless sensor networks
- circuit design
- energy consumption
- power consumption
- energy efficiency
- sensor networks
- power dissipation
- high speed
- logic circuits
- cmos technology
- multi core architecture
- base station
- data dissemination
- low power
- data gathering
- data aggregation
- data transmission
- cost effective
- high density
- multi hop
- routing protocol
- low cost
- battery powered
- low overhead
- management system
- data sets
- flip flops
- response time
- integrated circuit
- sensor nodes