Sadulla Shaik

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 9

Top Topics

Equivalent Circuit

Energy Efficient

Top Venues

Int. J. Syst. Assur. Eng. Manag.

J. Circuits Syst. Comput.

Publications

Menda Sreevani, Vallabhuni Vijay, Kancharapu Chaitanya, Chelle Radhika, Nandi Manjula, D. Radha Krishna Koushik, B. Sai Venumadhav, T. Sai Jaideep, Chandra Shaker Pittala, Sadulla Shaik
State-of-art design: data selectors using quantum-dot cellular automata. Int. J. Syst. Assur. Eng. Manag. 15 (3) (2024)
S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Vallabhuni Vijay, Chandra Shaker Pittala, K. Indira, S. Swathi
Design and analysis of a novel compact quaternary adder. Int. J. Syst. Assur. Eng. Manag. 15 (7) (2024)
S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Inapudi Vasavi, Vallabhuni Vijay, Chandra Shaker Pittala
1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages. Int. J. Syst. Assur. Eng. Manag. 15 (3) (2024)
Sadulla Shaik, Satish Kanapala, Vallabhuni Vijay, Chandra Shaker Pittala
Design and performance analysis of low power and energy-efficient vedic multipliers. Int. J. Syst. Assur. Eng. Manag. 14 (3) (2023)
Sadulla Shaik
Device-Circuit Interaction and Performance Benchmarking of Tunnel Transistor-Based Ex-OR Gates for Energy Efficient Computing. J. Circuits Syst. Comput. 29 (14) (2020)
Sadulla Shaik, Kalva Sri Rama Krishna, Mazhar Abbas, Munir Ahmed, Dinesh Mavaluru
Applying several soft computing techniques for prediction of bearing capacity of driven piles. Eng. Comput. 35 (4) (2019)
Sadulla Shaik, Kalva Sri Rama Krishna, Ramesh Vaddi
Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD. J. Circuits Syst. Comput. 27 (3) (2018)
Sadulla Shaik, Kalva Sri Rama Krishna
. Electron. Gov. an Int. J. 13 (4) (2017)
Sadulla Shaik, Kalva Sri Rama Krishna, Ramesh Vaddi
Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing. VLSI Design (2016)
Kasturi Subramanyam, Sadulla Shaik, Ramesh Vaddi
Tunnel FET based low voltage static vs dynamic logic families for energy efficiency. VDAT (2014)