Design and performance analysis of low power and energy-efficient vedic multipliers.
Sadulla ShaikSatish KanapalaVallabhuni VijayChandra Shaker PittalaPublished in: Int. J. Syst. Assur. Eng. Manag. (2023)
Keyphrases
- low power
- energy efficient
- power consumption
- single chip
- energy efficiency
- low cost
- digital signal processing
- high speed
- low power consumption
- vlsi architecture
- logic circuits
- gate array
- cmos technology
- power dissipation
- mixed signal
- power reduction
- energy consumption
- nm technology
- wireless sensor networks
- design methodology
- signal processing
- sensor networks
- energy saving
- real time
- multi hop
- base station
- routing protocol
- data sets