Abhijit R. Asati

Publication Activity (10 Years)

Years Active: 2008-2022
Publications (10 Years): 14

Top Topics

Fpga Implementation

Artificial Intelligence And Machine Learning

Top Venues

Microprocess. Microsystems

IET Image Process.

Int. J. Reconfigurable Comput.

Publications

Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis. Wirel. Pers. Commun. 127 (3) (2022)
Vineet Kumar, Abhijit R. Asati, Anu Gupta
Dedicated hardware architecture for localizing iris in VW images. J. King Saud Univ. Comput. Inf. Sci. 34 (7) (2022)
Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications. J. Ambient Intell. Humaniz. Comput. 12 (7) (2021)
Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications. Comput. Intell. 37 (3) (2021)
Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications. Circuits Syst. Signal Process. 40 (6) (2021)
Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm. Microprocess. Microsystems 80 (2021)
Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
Speed optimal FPGA implementation of the encryption algorithms for telecom applications. Microprocess. Microsystems 79 (2020)
Prateek Sikka, Abhijit R. Asati, Chandra Shekhar
High-Level synthesis assisted design and verification framework for automotive radar processors. Microprocess. Microsystems 78 (2020)
Vineet Kumar, Abhijit R. Asati, Anu Gupta
Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation. IET Image Process. 12 (10) (2018)
Vineet Kumar, Abhijit R. Asati, Anu Gupta
Hardware Accelerators for Iris Localization. J. Signal Process. Syst. 90 (4) (2018)
Vineet Kumar, Abhijit R. Asati, Anu Gupta
Low-latency median filter core for hardware implementation of 5 × 5 median filtering. IET Image Process. 11 (10) (2017)
Vineet Kumar, Abhijit R. Asati, Anu Gupta
A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images. J. Electr. Comput. Eng. 2016 (2016)
Priya Gupta, Anu Gupta, Abhijit R. Asati
Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region. Int. J. Reconfigurable Comput. 2015 (2015)
Vineet Kumar, Abhijit R. Asati, Anu Gupta
An Iris localization method for noisy infrared iris images. ICSIPA (2015)
Ankur Kumar, Abhijit R. Asati
Iris based biometric identification system. ICAILP (2014)
Deepak Bharti, Abhijit R. Asati
Design of a Static Current Simulator Using Device Matrix Approach. ISED (2012)
Subhendu Kumar Sahoo, Anu Gupta, Abhijit R. Asati, Chandra Shekhar
A Novel Redundant Binary Number to Natural Binary Number Converter. J. Signal Process. Syst. 59 (3) (2010)
Subhendu Kumar Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati, Anu Gupta
Dual channel addition based FFT processor architecture for signal and image processing. Int. J. High Perform. Syst. Archit. 2 (1) (2009)
Abhijit R. Asati, Subhendu Kumar Sahoo, Chandra Shekhar
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load. ICETET (2009)
Abhijit R. Asati, Chandrashekhar
An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier design using 0.6 μm CMOS TSPC logic design style. ICIIS (2008)