A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic.
Subhendu Kumar SahooAbhijit AshatiRasmita SahooChandra ShekharPublished in: ICETET (2008)
Keyphrases
- hardware implementation
- pipelined architecture
- high speed
- floating point
- parallel architecture
- processing elements
- signal processing
- efficient implementation
- floating point arithmetic
- field programmable gate array
- fpga implementation
- hardware design
- low power
- hardware architecture
- software implementation
- image processing algorithms
- real time
- dedicated hardware
- bit parallel
- memory management
- parallel implementation
- fourier transform
- pipeline architecture
- shift register
- parallel programming
- image binarization
- document images
- general purpose
- multiresolution