Implementation of a high speed multiplier for high-performance and low power applications.
G. Ganesh KumarSubhendu Kumar SahooPublished in: VDAT (2015)
Keyphrases
- low power
- high speed
- signal processor
- power consumption
- low cost
- low power consumption
- vlsi architecture
- single chip
- cmos technology
- wireless transmission
- high power
- hardware implementation
- ultra low power
- floating point
- frame rate
- logic circuits
- mixed signal
- vlsi circuits
- digital signal processing
- image sensor
- design considerations
- graphics processing units
- delay insensitive
- gate array
- efficient implementation