Sujit Kumar Patel

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 14

Top Topics

Adaptive Filter

Least Mean Square

Fast Fourier Transform

Energy Efficient

Top Venues

Turkish J. Electr. Eng. Comput. Sci.

J. Electron. Test.

IEEE Trans. Circuits Syst. II Express Briefs

IET Circuits Devices Syst.

Publications

Konudula Anjali Rao, Abhishek Kumar, Sujit Kumar Patel, Dmitry I. Kaplun, Neetesh Purohit
Design of Frequency Sampling Rational Rate Polyphase FIR Converter. IEEE Trans. Circuits Syst. II Express Briefs 71 (2) (2024)
Konudula Anjali Rao, Abhishek Kumar, Dmitrii I. Kaplun, Sujit Kumar Patel, Neetesh Purohit
Design of low complexity parallel polyphase finite impulse response filter using coefficient symmetry. IET Circuits Devices Syst. 17 (1) (2023)
Anuradha, Sujit Kumar Patel, Subodh Kumar Singhal
An area-delay efficient single-precision floating-point multiplier for VLSI systems. Microprocess. Microsystems 98 (2023)
Subodh Kumar Singhal, Sujit Kumar Patel, Anurag Mahajan, Gaurav Saxena
Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications. Turkish J. Electr. Eng. Comput. Sci. 29 (4) (2021)
Shireesh Kumar Rai, Rishikesh Pandey, Bharat Garg, Sujit Kumar Patel
A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth. Turkish J. Electr. Eng. Comput. Sci. 29 (1) (2021)
Bharat Garg, Sujit Kumar Patel
Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications. Wirel. Pers. Commun. 118 (2) (2021)
Bharat Garg, Sujit Kumar Patel
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency. J. Signal Process. Syst. 93 (1) (2021)
Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. J. Circuits Syst. Comput. 29 (12) (2020)
Sujit Kumar Patel, Subodh Kumar Singhal
Area-delay and energy efficient multi-operand binary tree adder. IET Circuits Devices Syst. 14 (5) (2020)
Bharat Garg, Sujit Kumar Patel, Sunil Dutt
LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing. J. Electron. Test. 36 (3) (2020)
Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai
An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic. J. Electron. Test. 36 (1) (2020)
Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai
A power and area efficient approximate carry skip adder for error resilient applications. Turkish J. Electr. Eng. Comput. Sci. 28 (1) (2020)
Sujit Kumar Patel, Bharat Garg, Anurag Mahajan, Shireesh Kumar Rai
Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems. iSES (2019)
Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Pramod Kumar Meher, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, Thambipillai Srikanthan
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2015)
Basant Kumar Mohanty, Sujit Kumar Patel
Efficient very large-scale integration architecture for variable length block least mean square adaptive filter. IET Signal Process. 9 (8) (2015)
Basant Kumar Mohanty, Sujit Kumar Patel
Area-Delay-Power Efficient Carry-Select Adder. IEEE Trans. Circuits Syst. II Express Briefs (6) (2014)