Basant K. Mohanty

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 9

Top Topics

Wavelet Transform

Adaptive Filter

Impulse Response

Least Mean Square

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Biomed. Signal Process. Control.

Publications

Rehan Ahmad, Basant K. Mohanty
A novel computing scheme based on pattern matching for identification of nephron loss and chronic kidney disease stage. Turkish J. Electr. Eng. Comput. Sci. 31 (7) (2023)
Rehan Ahmad, Basant K. Mohanty
Chronic kidney disease stage identification using texture analysis of ultrasound images. Biomed. Signal Process. Control. 69 (2021)
Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. J. Circuits Syst. Comput. 29 (12) (2020)
Basant K. Mohanty, Pramod Kumar Meher
Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Basant K. Mohanty, Vivek Chaturvedi, Vijeta Rathore, Thambipillai Srikanthan
Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems. DSP (2015)
Vivek Chaturvedi, Basant K. Mohanty, Thambipillai Srikanthan
Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systems. DSP (2015)
Carlo Safarian, Tokunbo Ogunfunmi, Walter J. Kozacky, Basant K. Mohanty
FPGA implementation of LMS-based FIR adaptive filter for real time digital signal processing applications. DSP (2015)
Basant K. Mohanty, Pramod Kumar Meher, Thambipillai Srikanthan
Critical-path optimization for efficient hardware realization of lifting and flipping DWTs. ISCAS (2015)
Pramod Kumar Meher, Basant K. Mohanty, Thambipillai Srikanthan
Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits. ISCAS (2014)
Basant K. Mohanty, Vikas Tiwari
Modified PEB Formulation for Hardware-Efficient Fixed-Width Booth Multiplier. Circuits Syst. Signal Process. 33 (12) (2014)
Basant K. Mohanty, Pramod Kumar Meher, Somaya Al-Máadeed, Abbes Amira
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2014)
Basant K. Mohanty, Pramod Kumar Meher
Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation. IET Image Process. 8 (6) (2014)
Basant K. Mohanty, Pramod Kumar Meher
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm. IEEE Trans. Signal Process. 61 (4) (2013)
Basant K. Mohanty, Anurag Mahajan
Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer. IET Circuits Devices Syst. 7 (6) (2013)
Basant K. Mohanty, Pramod Kumar Meher
Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT. IEEE Trans. Circuits Syst. Video Technol. 23 (2) (2013)
Basant K. Mohanty, Anurag Mahajan
Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT. J. Low Power Electron. 9 (1) (2013)
Basant K. Mohanty, Somaya Al-Máadeed, Abbes Amira
Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank. IDT (2013)
Basant K. Mohanty, Anurag Mahajan, Pramod Kumar Meher
Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT. IEEE Trans. Circuits Syst. II Express Briefs (7) (2012)
Basant K. Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal
Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform. ISCAS (2012)
Basant K. Mohanty, Pramod Kumar Meher
Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT. IEEE Trans. Signal Process. 59 (5) (2011)
Basant K. Mohanty, Pramod Kumar Meher
Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames. IEEE Trans. Signal Process. 59 (11) (2011)
Basant K. Mohanty, Pramod Kumar Meher
Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT. IEEE Trans. Circuits Syst. Video Technol. 20 (9) (2010)
Anurag Mahajan, Basant K. Mohanty
Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic. APCCAS (2010)
Basant K. Mohanty, Pramod Kumar Meher
Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. ASAP (2008)
Basant K. Mohanty, Pramod Kumar Meher
Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform. ASAP (2008)
Pramod Kumar Meher, Basant K. Mohanty, Jagdish Chandra Patra
Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs (2) (2008)
Basant K. Mohanty, Pramod Kumar Meher
Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform. APCCAS (2006)
Basant K. Mohanty, Pramod Kumar Meher
VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT. APCCAS (2006)