Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits.
Pramod Kumar MeherBasant K. MohantyThambipillai SrikanthanPublished in: ISCAS (2014)
Keyphrases
- single pass
- computational cost
- computationally efficient
- search space
- high efficiency
- experimental evaluation
- hardware implementation
- detection algorithm
- optimal solution
- preprocessing
- cost function
- dynamic programming
- optimization algorithm
- simulated annealing
- worst case
- computational complexity
- objective function
- real time
- times faster
- significant improvement
- k means
- probabilistic model
- matching algorithm
- similarity measure
- critical path
- particle swarm optimization
- high speed
- np hard
- multi objective
- evolutionary algorithm
- data structure
- neural network