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Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.
Subodh Kumar Singhal
Basant K. Mohanty
Sujit Kumar Patel
Gaurav Saxena
Published in:
J. Circuits Syst. Comput. (2020)
Keyphrases
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bit parallel
pattern matching
data flow
neural network
efficient implementation
parallel implementation
website
general purpose
computationally efficient
parallel computing
parallel architectures