Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT.

Basant K. Mohanty Anurag Mahajan

Published in: J. Low Power Electron. (2013)

Keyphrases

parallel architecture
parallel processing
hardware implementation
parallel implementation
processing elements
pairwise
neural network
efficient implementation
distributed memory
systolic array
synthetic aperture sonar
optimal solution
wavelet transform
hardware architecture
high level synthesis