Kavita Khare

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 12

Top Topics

Error Compensation

Power Reduction

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Embed. Syst. Lett.

Publications

Zainab Aizaz, Kavita Khare, Aizaz Tirmizi
Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs. IEEE Embed. Syst. Lett. 16 (2) (2024)
Zainab Aizaz, Kavita Khare, Aizaz Tirmizi
FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications. FCCM (2023)
Zainab Aizaz, Kavita Khare
ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 70 (12) (2023)
Zainab Aizaz, Kavita Khare, Mohd Anas Khan, Mahesh Kumar Singh, Vaithiyanathan Dhandapani
A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs. APCCAS (2023)
Zainab Aizaz, Kavita Khare
Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Zainab Aizaz, Kavita Khare
Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error. Int. J. Circuit Theory Appl. 50 (6) (2022)
Divya Gautam, Kavita Khare, Bhavana P. Shrivastava
A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique. IEEE Access 9 (2021)
Ajay Kumar Dadoria, Kavita Khare
Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology. Circuits Syst. Signal Process. 38 (9) (2019)
Ajay Kumar Dadoria, Kavita Khare, Tarun Kumar Gupta, R. P. Singh
New Leakage Reduction Techniques for FinFET Technology with Its Application. J. Circuits Syst. Comput. 27 (7) (2018)
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
Concept, Design, and Implementation of Reconfigurable CORDIC. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Ajay Kumar Dadoria, Kavita Khare, R. P. Singh
Leakage Power Reduction Technique by using FinFET Technology. ICTCS (2016)
Shailesh Dwivedi, Kavita Khare, Ajay Kumar Dadoria
Low-Power High Speed 1-bit Full Adder Circuit Design. ICTCS (2016)
Supriya Aggarwal, Kavita Khare
Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline. VLSI Design (2013)
Supriya Aggarwal, Kavita Khare
CORDIC-based window implementation to minimise area and pipeline depth. IET Signal Process. 7 (5) (2013)
Tarun Kumar Gupta, Kavita Khare
Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits. Circuits Syst. Signal Process. 32 (6) (2013)
Supriya Aggarwal, Kavita Khare
Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence. J. Signal Process. Syst. 70 (1) (2013)
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2013)
Anita Jain, Kavita Khare
3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter. VDAT (2013)
Sunanda Manke, Kavita Khare, S. D. Sapre
FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems. J. Signal Process. Syst. 67 (2) (2012)
Supriya Aggarwal, Kavita Khare
Hardware Efficient Architecture for Generating Sine/Cosine Waves. VLSI Design (2012)
Supriya Aggarwal, Kavita Khare
Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm. Comput. J. 55 (5) (2012)
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Supriya Aggarwal, Kavita Khare
Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency. Int. J. Reconfigurable Comput. 2012 (2012)
Sunanda Manke, Kavita Khare, S. D. Sapre
VCAT synchroniser - reduction of buffer size in VCAT enabled next generation SDH networks. Eur. Trans. Telecommun. 22 (8) (2011)
J. Deshmukh, Kavita Khare
Standby leakage reduction in nanoscale CMOS VLSI circuits. ICWET (2010)
Vikas Gupta, Kavita Khare, R. P. Singh
FPGA Design and Implementation Issues of Artificial Neural Network Based PID Controllers. ARTCom (2009)
Sunanda Manke, Kavita Khare, S. D. Sapre
Differential Delay Compensator -- A New Approach to Reduce Buffer Size in VCAT Enabled Next Generation SDH Networks. ARTCom (2009)
Sunanda Manke, Kavita Khare, S. D. Sapre
100Mbps Ethernet data transmission over SDH networks using Cross Virtual Concatenation. ICON (2008)