Tarun Kumar Gupta

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 17

Top Topics

Top Venues

Microelectron. J.

Int. J. Circuit Theory Appl.

Circuits Syst. Signal Process.

J. Circuits Syst. Comput.

Publications

Alok Kumar, Tarun Kumar Gupta, Bhavana P. Shrivastava, Abhinav Gupta
Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems. Microelectron. J. 136 (2023)
Alok Kumar, Tarun Kumar Gupta, Bhavana P. Shrivastava, Abhinav Gupta
Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs. Microelectron. J. 134 (2023)
Sichen Pan, Tarun Kumar Gupta, Khalid Raza
BatTS: a hybrid method for optimizing deep feedforward neural network. PeerJ Comput. Sci. 9 (2023)
Yogesh Shrivastava, Tarun Kumar Gupta
Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor. J. Circuits Syst. Comput. 31 (5) (2022)
Tarun Kumar Gupta, Khalid Raza
Optimization of Artificial Neural Network: A Bat Algorithm-Based Approach. ISDA (2021)
Tarun Kumar Gupta, Khalid Raza
Optimizing Deep Feedforward Neural Network Architecture: A Tabu Search Based Approach. Neural Process. Lett. 51 (3) (2020)
Sandeep Garg, Tarun Kumar Gupta, Amit Kumar Pandey
A 1-bit full adder using CNFET based dual chirality high speed domino logic. Int. J. Circuit Theory Appl. 48 (1) (2020)
Pramod Kumar Patel, M. M. Malik, Tarun Kumar Gupta
A novel high-density dual threshold GNRFET SRAM design with improved stability. Microprocess. Microsystems 73 (2020)
Sandeep Garg, Tarun Kumar Gupta
FDSTDL: Low-power technique for FinFET domino circuits. Int. J. Circuit Theory Appl. 47 (6) (2019)
Vijay Kumar Magraiya, Tarun Kumar Gupta
ONOFIC-based leakage reduction technique for FinFET domino circuits. Int. J. Circuit Theory Appl. 47 (2) (2019)
Sandeep Garg, Tarun Kumar Gupta
Low leakage domino logic circuit for wide fan-in gates using CNTFET. IET Circuits Devices Syst. 13 (2) (2019)
Pramod Kumar Patel, M. M. Malik, Tarun Kumar Gupta
Performance evaluation of single-ended disturb-free CNTFET-based multi-Vt SRAM. Microelectron. J. 90 (2019)
Vijay Kumar Magraiya, Tarun Kumar Gupta
ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction. Circuits Syst. Signal Process. 38 (6) (2019)
Sandeep Garg, Tarun Kumar Gupta
A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology. J. Circuits Syst. Comput. 28 (10) (2019)
Ajay Kumar Dadoria, Kavita Khare, Tarun Kumar Gupta, R. P. Singh
New Leakage Reduction Techniques for FinFET Technology with Its Application. J. Circuits Syst. Comput. 27 (7) (2018)
Tarun Kumar Gupta, Khalid Raza
Optimizing Deep Neural Network Architecture: A Tabu Search Based Approach. CoRR (2018)
Amit Kumar Pandey, Pawan Kumar Verma, Rajesh Verma, Tarun Kumar Gupta
Analysis of Noise Immunity for Wide OR Footless Domino Circuit Using Keeper Controlling Network. Circuits Syst. Signal Process. 37 (10) (2018)
Nidhi Handa, Tarun Kumar Gupta, S. L. Singh
Comparative Study of Bakhshālī Square Root Method with Newton's Iterative Method. SocProS (1) (2015)
Ram Murti Rawat, Tarun Kumar Gupta, Mohammad Sajid, Shiv Prakash, Dinesh Prasad Sahu, Sohan Kumar Yadav, Chanchal Kumar
An Improved Fuzzy Voting Scheme for Fault Tolerant Systems. Int. J. Appl. Evol. Comput. 6 (2) (2015)
Tarun Kumar Gupta, Kavita Khare
Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits. Circuits Syst. Signal Process. 32 (6) (2013)