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Sandeep Garg
ORCID
Publication Activity (10 Years)
Years Active: 2019-2020
Publications (10 Years): 4
Top Topics
Logic Circuits
Delay Insensitive
High Speed
Low Power Consumption
Top Venues
Int. J. Circuit Theory Appl.
IET Circuits Devices Syst.
J. Circuits Syst. Comput.
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Publications
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Sandeep Garg
,
Tarun Kumar Gupta
,
Amit Kumar Pandey
A 1-bit full adder using CNFET based dual chirality high speed domino logic.
Int. J. Circuit Theory Appl.
48 (1) (2020)
Sandeep Garg
,
Tarun Kumar Gupta
FDSTDL: Low-power technique for FinFET domino circuits.
Int. J. Circuit Theory Appl.
47 (6) (2019)
Sandeep Garg
,
Tarun Kumar Gupta
Low leakage domino logic circuit for wide fan-in gates using CNTFET.
IET Circuits Devices Syst.
13 (2) (2019)
Sandeep Garg
,
Tarun Kumar Gupta
A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology.
J. Circuits Syst. Comput.
28 (10) (2019)