Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters.
Pramod Kumar MeherBasant Kumar MohantyM. N. S. SwamyPublished in: VLSI Design (2015)
Keyphrases
- low power
- reconfigurable architecture
- low power consumption
- power consumption
- low cost
- high speed
- systolic array
- single chip
- impulse response
- fir filters
- digital signal processing
- logic circuits
- wireless transmission
- cmos technology
- image processing
- high power
- image sensor
- real time
- power dissipation
- vlsi architecture
- edge detection
- vlsi circuits
- gate array
- filter design
- wavelet transform
- nm technology