Mitra Mirhassani

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 39

Top Topics

Fpga Implementation

Continuous Valued

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Saad Pola, Marko Jovanovic, Maher A. Azzouz, Mitra Mirhassani
Cyber Resiliency Enhancement of Overcurrent Relays in Distribution Systems. IEEE Trans. Smart Grid 15 (4) (2024)
Madhan Thirumoorthi, Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid
). IEEE Trans. Very Large Scale Integr. Syst. 32 (8) (2024)
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
Digital Hardware Implementations of Spiking Neural Networks With Selective Input Sparsity for Edge Inferences in Controlled Image Acquisition Environments. IEEE Trans. Circuits Syst. II Express Briefs 70 (5) (2023)
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron. IEEE Trans. Very Large Scale Integr. Syst. 31 (9) (2023)
Madhan Thirumoorthi, Alexander J. Leigh, Moslem Heidarpur, Mohammed A. S. Khalid, Mitra Mirhassani
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations. IEEE Trans. Very Large Scale Integr. Syst. 31 (10) (2023)
Foroogh Behnia, Habib Zare Ahmadabadi, Beth-Anne Schuelke Leech, Mitra Mirhassani
Developing a fuzzy optimized model for selecting a maintenance strategy in the paper industry: An integrated FGP-ANP-FMEA approach. Expert Syst. Appl. 232 (2023)
Edris Zaman Farsa, Moslem Heidarpur, Arash Ahmadi, Mitra Mirhassani
High-Performance FPGA Implementation of Fully Connected Networks of SAM Neurons. ISCAS (2023)
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
Selective Input Sparsity in Spiking Neural Networks for Pattern Classification. ISCAS (2022)
Moslem Heidarpur, Mitra Mirhassani
Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation". IEEE Trans. Very Large Scale Integr. Syst. 30 (1) (2022)
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
A High-Accuracy Digital Implementation of the Morris-Lecar Neuron With Variable Physiological Parameters. IEEE Trans. Circuits Syst. II Express Briefs 69 (10) (2022)
Madhan Thirumoorthi, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 30 (5) (2022)
Hamidreza Esmaeili Taheri, Mitra Mirhassani
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach. IEEE Trans. Very Large Scale Integr. Syst. 30 (3) (2022)
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
A Low-Resource Digital Implementation of the Fitzhugh-Nagumo Neuron. PRIME (2022)
Neda Rezaei, Mitra Mirhassani
Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference. Microelectron. J. 113 (2021)
Moslem Heidarpur, Mitra Mirhassani
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation. IEEE Trans. Very Large Scale Integr. Syst. 29 (4) (2021)
Madhan Thirumoorthi, Marko Jovanovic, Mitra Mirhassani, Mohammed A. S. Khalid
Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF. IEEE Trans. Very Large Scale Integr. Syst. 29 (11) (2021)
Alexander J. Leigh, Mitra Mirhassani, Roberto Muscedere
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model. ISCAS (2020)
Alexander J. Leigh, Mitra Mirhassani, Roberto Muscedere
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model. IEEE Trans. Circuits Syst. (12) (2020)
Iman Y. Taha, Mitra Mirhassani
A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar. IEEE Trans. Very Large Scale Integr. Syst. 27 (10) (2019)
Bahar Youssefi, Alexander J. Leigh, Mitra Mirhassani, Q. M. Jonathan Wu
Tunable Neuron With PWL Approximation Based on the Minimum Operator. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Iman Y. Taha, Mitra Mirhassani
A Varactor-Less DCO With 7GHz Tuning Range for 77GHz Automotive Radars. IEEE Access 7 (2019)
Babak Zamanlooy, Mitra Mirhassani, Majid Ahmadi
Review of Arithmetic Operations Using the Continuous Valued Number System. MWSCAS (2018)
Iman Y. Taha, Mitra Mirhassani, Arezoo Emadi
A Monotonically Linear DCO for 77 GHz Automotive Radars. MWSCAS (2018)
Bahar Youssefi, Alexander J. Leigh, Mitra Mirhassani, Q. M. Jonathan Wu
Hardware Realization of Mixed-Signal Neural Networks with Modular Synapse-Neuron arrays. ISCAS (2018)
Yuan Jing, Bahar Youssefi, Mitra Mirhassani, Roberto Muscedere
An efficient FPGA implementation of Optical Character Recognition for License Plate Recognition. CCECE (2017)
Seyed Mahmoud Anisheh, Hossein Shamsi, Mitra Mirhassani
Positive feedback technique and split-length transistors for DC-gain enhancement of two-stage op-amps. IET Circuits Devices Syst. 11 (6) (2017)
Babak Zamanlooy, Mitra Mirhassani
Mixed-signal VLSI neural network based on Continuous Valued Number System. Neurocomputing 221 (2017)
Esrafil Jedari, Rashid Rashidzadeh, Mitra Mirhassani, Majid Ahmadi
Two-electrode ECG measurement circuit using a feed forward CMRR enhancement method. CCECE (2017)
Roberto Muscedere, Mitra Mirhassani
A software tool for generating optimized multipartite table parameters. CCECE (2017)
Iman Y. Taha, Mitra Mirhassani
A CMOS differential DCO with amplitude stabilization for 24GHz automotive radars. CCECE (2017)
Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi
A neural network architecture using high resolution multiplying digital to analog converters. MWSCAS (2017)
Babak Zamanlooy, Mitra Mirhassani
An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Shaghayegh Gomar, Mitra Mirhassani, Majid Ahmadi
Precise digital implementations of hyperbolic tanh and sigmoid function. ACSSC (2016)
Bahar Youssefi, Mitra Mirhassani, Q. M. Jonathan Wu
Efficient mixed-signal synapse multipliers for multi-layer feed-forward neural networks. MWSCAS (2016)
Iman Y. Taha, Mitra Mirhassani
A 24GHz Digitally Controlled Oscillator for automotive radar in 65nm CMOS. ISCAS (2016)
Hadis Takalo, Arash Ahmadi, Mitra Mirhassani, Majid Ahmadi
Analog cellular neural network for application in physical unclonable functions. ISCAS (2016)
Shaghayegh Gomar, Mitra Mirhassani, Majid Ahmadi, Mehrdad Saif
A digital neuromorphic circuit for neural-glial interaction. IJCNN (2016)
Babak Zamanlooy, Mitra Mirhassani
CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning. IEEE Trans. Very Large Scale Integr. Syst. 23 (11) (2015)
Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi
A modular mixed-signal CVNS neural network architecture. IJCNN (2015)
Iman Y. Taha, Mitra Mirhassani
A temperature compensated relaxation oscillator for SoC implementations. NEWCAS (2014)
Shaghayegh Gomar, Arash Ahmadi, Shahpour Alirezaee, Majid Ahmadi, Mitra Mirhassani
A low cost biomimetic implementation of a CPG based on AdEx neuron model. ICECS (2014)
Babak Zamanlooy, Mitra Mirhassani
Area efficient low-sensitivity lumped madaline based on Continuous Valued Number System. ISCAS (2014)
Babak Zamanlooy, Mitra Mirhassani
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Babak Zamanlooy, Mitra Mirhassani
Area-efficient robust Madaline based on continuous valued number system. Neurocomputing 140 (2014)
Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi
A Fault-Tolerant Area-Efficient Current-Mode ADC for Multiple-Valued Neural Networks. ISMVL (2012)
Babak Zamanlooy, Ashley Novak, Mitra Mirhassani
Complexity Study of the Continuous Valued Number System Adders. ISMVL (2012)
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
A Prototype CVNS Distributed Neural Network Using Synapse-Neuron Modules. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2012)
Babak Zamanlooy, Mitra Mirhassani
Efficient hardware implementation of threshold neural networks. NEWCAS (2012)
Ashley Novak, Farinoush Saffar, Mitra Mirhassani, Huapeng Wu
Current mode multiple-valued adder for cryptography processors. ISCAS (2012)
Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien
Error Recovery in Continuous Valued Number System. J. Circuits Syst. Comput. 20 (8) (2011)
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
A study on resistive-type truncated CVNS Distributed Neural Networks. ISCAS (2011)
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Mitra Mirhassani, Babak Zamanlooy
System-level design of low complexity CVNS feed forward neural network. ISCAS (2010)
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
Resistive-Type CVNS Distributed Neural Networks With Improved Noise-to-Signal Ratio. IEEE Trans. Circuits Syst. II Express Briefs (10) (2010)
Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi
16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin. ISMVL (2009)
Mitra Mirhassani
Mixed-signal CVNS adder for two-operand binary addition. EIT (2009)
Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi
An area-speed efficient method for current mode analog to digital converters. ECCTD (2009)
Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi
Current-mode Multiple-valued Dynamic Memory. ISCAS (2009)
Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien
Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing. IEEE Trans. Very Large Scale Integr. Syst. 16 (9) (2008)
Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien
Robust analog neural network based on continuous valued number system. ISCAS (2008)
Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien
Digital Multiplication using Continuous Valued Digits. ISCAS (2007)
Mitra Mirhassani, Majid Ahmadi, William C. Miller
A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays. VLSI (2003)