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Sewook Hwang
Publication Activity (10 Years)
Years Active: 2011-2021
Publications (10 Years): 14
Top Topics
Cmos Technology
Acquisition Process
Clock Frequency
Class Noise
Top Venues
IEEE Trans. Very Large Scale Integr. Syst.
IEEE Trans. Circuits Syst. I Regul. Pap.
ISSCC
IEEE Trans. Circuits Syst. II Express Briefs
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Publications
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Junyoung Song
,
Sewook Hwang
,
Chulwoo Kim
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
29 (8) (2021)
Yoonjae Choi
,
Sewook Hwang
,
Yeonho Lee
,
Hyunsu Park
,
Jonghyuck Choi
,
Jincheol Sim
,
Chulwoo Kim
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector.
IEEE Access
9 (2021)
Nevada Sanchez
,
Kailiang Chen
,
Chao Chen
,
Dan McMahill
,
Sewook Hwang
,
Joseph Lutsky
,
Jungwook Yang
,
Liewei Bao
,
Leung Kin Chiu
,
Graham Peyton
,
Hamid Soleimani
,
Bob Ryan
,
J. R. Petrus
,
Youn-Jae Kook
,
Tyler S. Ralston
,
Keith Fife
,
Jonathan Rothberg
34.1 An 8960-Element Ultrasound-on-Chip for Point-of-Care Ultrasound.
ISSCC
(2021)
Yeonho Lee
,
Yoonjae Choi
,
Junyoung Song
,
Sewook Hwang
,
Sang-Geun Bae
,
Jaehun Jun
,
Chulwoo Kim
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
IEEE J. Solid State Circuits
54 (2) (2019)
Sang-Geun Bae
,
Sewook Hwang
,
Junyoung Song
,
Yeonho Lee
,
Chulwoo Kim
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs
(2) (2019)
Junyoung Song
,
Sewook Hwang
,
Hyun-Woo Lee
,
Chulwoo Kim
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
(1) (2018)
Jayoung Kim
,
Junyoung Song
,
Jungtaek You
,
Sewook Hwang
,
Sang-Geun Bae
,
Chulwoo Kim
A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs
(6) (2017)
Sewook Hwang
,
Junyoung Song
,
Yeonho Lee
,
Chulwoo Kim
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap.
(10) (2017)
Yeonho Lee
,
Yoonjae Choi
,
Sang-Geun Bae
,
Jaehun Jun
,
Junyoung Song
,
Sewook Hwang
,
Chulwoo Kim
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
ISSCC
(2017)
Junyoung Song
,
Hyun-Woo Lee
,
Sewook Hwang
,
Chulwoo Kim
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique.
IEEE Trans. Very Large Scale Integr. Syst.
25 (1) (2017)
Sewook Hwang
,
Sungjun Moon
,
Junyoung Song
,
Chulwoo Kim
A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE.
VLSI Circuits
(2016)
Sewook Hwang
,
Junyoung Song
,
Sang-Geun Bae
,
Yeonho Lee
,
Chulwoo Kim
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers.
IEEE Trans. Very Large Scale Integr. Syst.
24 (3) (2016)
Junyoung Song
,
Sewook Hwang
,
Chulwoo Kim
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels.
IEEE Trans. Very Large Scale Integr. Syst.
24 (8) (2016)
Junyoung Song
,
Hyun-Woo Lee
,
Jayoung Kim
,
Sewook Hwang
,
Chulwoo Kim
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces.
ISSCC
(2015)
Junyoung Song
,
Sewook Hwang
,
Hyun-Woo Lee
,
Chulwoo Kim
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs
(11) (2014)
Kyeong-Min Kim
,
Sewook Hwang
,
Junyoung Song
,
Chulwoo Kim
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator.
IEEE Trans. Very Large Scale Integr. Syst.
22 (10) (2014)
Sewook Hwang
,
Kyeong-Min Kim
,
Jungmoon Kim
,
Seon Wook Kim
,
Chulwoo Kim
A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor.
IEEE Trans. Very Large Scale Integr. Syst.
21 (3) (2013)
Junyoung Song
,
Hyun-Woo Lee
,
Soo-Bin Lim
,
Sewook Hwang
,
Yunsaing Kim
,
Young-Jung Choi
,
Byong-Tae Chung
,
Chulwoo Kim
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface.
ISSCC
(2013)
Sewook Hwang
,
Jabeom Koo
,
Kisoo Kim
,
Hokyu Lee
,
Chulwoo Kim
500 µW 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap.
(9) (2013)
Young-Ho Kwak
,
Yongtae Kim
,
Sewook Hwang
,
Chulwoo Kim
A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
(2) (2013)
Junyoung Song
,
Inhwa Jung
,
Minyoung Song
,
Young-Ho Kwak
,
Sewook Hwang
,
Chulwoo Kim
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection.
IEEE Trans. Circuits Syst. I Regul. Pap.
(2) (2013)
Junyoung Song
,
Hyun-Woo Lee
,
Sewook Hwang
,
Inhwa Jung
,
Chulwoo Kim
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process.
ASP-DAC
(2013)
Sewook Hwang
,
Inhwa Jung
,
Junyoung Song
,
Chulwoo Kim
A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS.
ISCAS
(2012)
Sewook Hwang
,
Minyoung Song
,
Young-Ho Kwak
,
Inhwa Jung
,
Chulwoo Kim
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile.
IEEE J. Solid State Circuits
47 (5) (2012)
Sewook Hwang
,
Minyoung Song
,
Young-Ho Kwak
,
Inhwa Jung
,
Chulwoo Kim
3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS.
ISSCC
(2011)