A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard.

Liang Hong Weifeng He Hui Zhu Zhigang Mao

Published in: IEICE Electron. Express (2013)

Keyphrases

low power
vlsi architecture
block size
power consumption
high speed

low cost
low complexity
mode decision
discrete cosine transform
video coding standard

vlsi implementation
real time
quadtree
intra prediction
bit rate

image processing
dct domain
video compression
high resolution
digital images