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Qin Wang
ORCID
Publication Activity (10 Years)
Years Active: 2011-2024
Publications (10 Years): 36
Top Topics
Random Number Generator
Neural Network
Remote Sensing
Sigmoid Function
Top Venues
ASICON
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
ASPDAC
IEEE Trans. Very Large Scale Integr. Syst.
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Publications
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Kunyue Li
,
Zhengji Zhao
,
Qixuan Cai
,
Qin Wang
,
Naifeng Jing
,
Zhigang Mao
,
Jianfei Jiang
A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance.
Expert Syst. Appl.
249 (2024)
Chen Yin
,
Jianfei Jiang
,
Qin Wang
,
Zhigang Mao
,
Naifeng Jing
SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration.
ASPDAC
(2024)
Lin Xie
,
Zizheng Dong
,
Jialei Sun
,
Sai Gao
,
Shuaipeng Li
,
Naifeng Jing
,
Qin Wang
,
Jianfei Jiang
A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction.
ISCAS
(2024)
Zihan Zhang
,
Jianfei Jiang
,
Qin Wang
,
Zhigang Mao
,
Naifeng Jing
3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
43 (1) (2024)
Chen Yin
,
Jianfei Jiang
,
Qin Wang
,
Zhigang Mao
,
Naifeng Jing
DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
43 (4) (2024)
Liyan Chen
,
Jianfei Jiang
,
Qin Wang
,
Zhigang Mao
,
Naifeng Jing
Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture.
ASPDAC
(2024)
Duo Yu
,
Ang Li
,
Naifeng Jing
,
Jianfei Jiang
,
Weiguang Sheng
,
Qin Wang
VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks.
ACM Great Lakes Symposium on VLSI
(2024)
Yanan Sun
,
Zhi Li
,
Weiyi Liu
,
Weifeng He
,
Qin Wang
,
Zhigang Mao
BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars.
IEEE Trans. Circuits Syst. I Regul. Pap.
70 (5) (2023)
Jianing Gao
,
Qiming Shao
,
Fangyu Deng
,
Qin Wang
,
Naifeng Jing
,
Jianfei Jiang
An NoC-based CNN Accelerator for Edge Computing.
ASICON
(2023)
Pengyu Liu
,
Zihan Zhang
,
Chen Yin
,
Liyan Chen
,
Jianfei Jiang
,
Qin Wang
,
Zhigang Mao
,
Naifeng Jing
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.
FPL
(2023)
Zhuo Chen
,
Zihan Zhang
,
Jianfei Jiang
,
Weiguang Sheng
,
Qin Wang
,
Naifeng Jing
ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator.
ASICON
(2023)
Naifeng Jing
,
Zihan Zhang
,
Yongshuai Sun
,
Pengyu Liu
,
Liyan Chen
,
Qin Wang
,
Jianfei Jiang
Exploiting bit sparsity in both activation and weight in neural networks accelerators.
Integr.
88 (2023)
Bingxi Pei
,
Shi Xu
,
Zhang Luo
,
Qin Wang
,
Mingche Lai
,
Weifeng He
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router.
IEEE Trans. Circuits Syst. II Express Briefs
70 (10) (2023)
Haifeng Xiang
,
Naifeng Jing
,
Jianfei Jiang
,
Hongbo Guo
,
Weiguang Sheng
,
Zhigang Mao
,
Qin Wang
RTMDet-R2: An Improved Real-Time Rotated Object Detector.
PRCV (12)
(2023)
Chen Yin
,
Naifeng Jing
,
Jianfei Jiang
,
Qin Wang
,
Zhigang Mao
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
42 (3) (2023)
Shuya Ji
,
Weidong Yang
,
Jianfei Jiang
,
Naifeng Jing
,
Weiguang Sheng
,
Ang Li
,
Qin Wang
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors.
ICCD
(2023)
Shengzhao Li
,
Qin Wang
,
Jianfei Jiang
,
Weiguang Sheng
,
Naifeng Jing
,
Zhigang Mao
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
30 (11) (2022)
Zihan Zhang
,
Jianfei Jiang
,
Yongxin Zhu
,
Qin Wang
,
Zhigang Mao
,
Naifeng Jing
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
41 (7) (2022)
Guochao Deng
,
Qin Wang
,
Jianfei Jiang
,
Qirun Hong
,
Naifeng Jing
,
Weiguang Sheng
,
Zhigang Mao
A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images.
IEEE Geosci. Remote. Sens. Lett.
19 (2022)
Taozhong Li
,
Naifeng Jing
,
Jianfei Jiang
,
Qin Wang
,
Zhigang Mao
,
Yiran Chen
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.
ACM Trans. Design Autom. Electr. Syst.
27 (6) (2022)
Zihan Zhang
,
Taozhong Li
,
Ning Guan
,
Qin Wang
,
Guanghui He
,
Weiguang Sheng
,
Zhigang Mao
,
Naifeng Jing
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration.
ACM Great Lakes Symposium on VLSI
(2020)
Zhongyuan Zhao
,
Weiguang Sheng
,
Qin Wang
,
Wenzhi Yin
,
Pengfei Ye
,
Jinchao Li
,
Zhigang Mao
Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.
IEEE Trans. Parallel Distributed Syst.
31 (9) (2020)
Yijia Zhang
,
Weiguang Sheng
,
Jian-Fei Jiang
,
Naifeng Jing
,
Qin Wang
,
Zhigang Mao
Priority Branches for Ship Detection in Optical Remote Sensing Images.
Remote. Sens.
12 (7) (2020)
Qin Wang
,
Fengyi Shen
,
Linyao Shen
,
Jia Huang
,
Weiguang Sheng
Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network.
J. Digit. Imaging
32 (6) (2019)
Yanan Sun
,
Jiawei Gu
,
Weifeng He
,
Qin Wang
,
Naifeng Jing
,
Zhigang Mao
,
Weikang Qian
,
Li Jiang
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.
IEEE Trans. Circuits Syst. II Express Briefs
(5) (2019)
Yue Zhao
,
Tong Li
,
Feng Dong
,
Qin Wang
,
Weifeng He
,
Jian-Fei Jiang
A New Approximate Multiplier Design for Digital Signal Processing.
ASICON
(2019)
Qin Wang
,
Zechen Liu
,
Jian-Fei Jiang
,
Naifeng Jing
,
Weiguang Sheng
A New Cellular-Based Redundant TSV Structure for Clustered Faults.
IEEE Trans. Very Large Scale Integr. Syst.
27 (2) (2019)
Taozhong Li
,
Qin Wang
,
Yongxin Zhu
,
Jian-Fei Jiang
,
Guanghui He
,
Jing Jin
,
Zhigang Mao
,
Naifeng Jing
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.
ACM Trans. Design Autom. Electr. Syst.
24 (2) (2019)
Sijie Zheng
,
Hongjun You
,
Guanghui He
,
Qin Wang
,
Tao Si
,
Jian-Fei Jiang
,
Jing Jin
,
Naifeng Jing
A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.
ISCAS
(2019)
Shuai Xie
,
Zhongyuan Zhao
,
Weiguang Sheng
,
Qin Wang
,
Zhigang Mao
MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.
ReConFig
(2018)
Zhongyuan Zhao
,
Yantao Liu
,
Weiguang Sheng
,
Tushar Krishna
,
Qin Wang
,
Zhigang Mao
Optimizing the data placement and transformation for multi-bank CGRA computing system.
DATE
(2018)
Jianfei Wang
,
Qin Wang
,
Li Jiang
,
Chao Li
,
Xiaoyao Liang
,
Naifeng Jing
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs.
IEEE Trans. Parallel Distributed Syst.
29 (3) (2018)
Xianjie Long
,
Qin Wang
,
Jian-Fei Jiang
,
Nin Guan
An on-chip circuit for timing measurement of SRAM IP.
ASICON
(2017)
Qin Wang
,
Zhenyang Chen
,
Jian-Fei Jiang
,
Zheng Guo
,
Zhigang Mao
Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC.
Integr.
59 (2017)
Chaoyang Li
,
Qin Wang
,
Jian-Fei Jiang
,
Nin Guan
A metastability-based true random number generator on FPGA.
ASICON
(2017)
Jian-Fei Jiang
,
Zhigang Mao
,
Weiguang Sheng
,
Qin Wang
,
Weifeng He
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.
J. Circuits Syst. Comput.
25 (10) (2016)
Jiachao Chen
,
Qin Wang
,
Zheng Guo
,
Junrong Liu
,
Haihua Gu
A Circuit Design of SMS4 against Chosen Plaintext Attack.
CIS
(2015)
Jiayi Hu
,
Qin Wang
,
Jian-Fei Jiang
,
Jing Xie
,
Zhigang Mao
A crosstalk avoidance scheme based on re-layout of signal TSV.
ASICON
(2015)
Jian-Fei Jiang
,
Weifeng He
,
Jizeng Wei
,
Qin Wang
,
Zhigang Mao
Design optimization for capacitive-resistively driven on-chip global interconnect.
IEICE Electron. Express
12 (8) (2015)
Jian-Fei Jiang
,
Weiguang Sheng
,
Qin Wang
,
Zhigang Mao
A contactless testing methodology for pre-bond interposer.
MWSCAS
(2015)
Sai Hu
,
Qin Wang
,
Zheng Guo
,
Jing Xie
,
Zhigang Mao
Fault detection and redundancy design for TSVs in 3D ICs.
ASICON
(2015)
Jieliang Lu
,
Qin Wang
,
Jing Xie
,
Zhigang Mao
TSVs-aware floorplanning for 3D integrated circuit.
ASICON
(2013)
Zhenyang Chen
,
Qin Wang
,
Jing Xie
,
Jin Tian
,
Jian-Fei Jiang
,
Yufei Li
,
Wen Yin
Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling.
ISCAS
(2013)
Shunqing Yan
,
Yongxin Zhu
,
Qiannan Zhang
,
Qin Wang
,
Ming Ni
,
Guangwei Xie
A Case Study of CPNS Intelligence: Provenance Reasoning over Tracing Cross Contamination in Food Supply Chain.
ICDCS Workshops
(2012)
Shunqing Yan
,
Liang Hong
,
Weifeng He
,
Qin Wang
Group-Based Fast Mode Decision Algorithm for Intra Prediction in HEVC.
SITIS
(2012)
Can Wang
,
Qin Wang
,
Jian-Fei Jiang
A new asynchronous delay-insensitive link based on a 1-of-4 LETS code.
ASICON
(2011)
Yuliang Tao
,
Guanghui He
,
Weifeng He
,
Qin Wang
,
Jun Ma
,
Zhigang Mao
Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems.
ISCAS
(2011)